The MC-11 is an unfinished project to create an SBC that is mostly compatible with the TRS-80 MC-10.
MCU 68HC11E1
The main component of this microcomputer is the E1 version of the Motorola 68HC11 micro controller. This is a 52-pin PLCC integrated circuit which provides address, data, and miscellaneous control signals. All timing in the system is derived from a 14.31818 MHz oscillator. The 68HC11 MCU is clocked at either 3.579 MHz or 7.159 MHz as provided by frequency divider logic in the Xilinx CPLD. The MCU further divides this by 4 to produce an operating frequency of either 0.89 MHz or 1.78 MHz. This frequency is available as the processor clock E.
The 68HC11 is designed to be used in a minimum hardware configuration so, a number of I/O lines are provided directly on the chip. In the MC-11 computer these I/O lines are used to receive timing signals from the Video Display Generator, receive data from the PS2 keyboard controller, support data storage/retrieval on an SD card and provide a bit-banged serial I/O port.
The 68HC11 operates in Expanded Mode with 512 bytes of internal RAM, 512 bytes of internal EEPROM, a full 16 line address bus and an 8 bit data bus which is multiplexed with the lower eight address lines. De-multiplexing of the address/data lines is performed by the CPLD during the low portion of the E clock. The Address Strobe signal (AS) provided by the MCU is not used in this system. Instead, the CPLD uses the clock divider logic along with feedback from the processor E clock to determine the correct time for latching the address lines.
VDG
The video interface function in the MC-11 is performed by the Motorola 6847 along with an MC1372 to produce NTSC composite output. The 6847 is a video display generator that will produce nine colors (eight colors and black), an alphanumeric display mode, and several graphics modes. In the MC-11 the VDG is interfaced to the 32K static RAM and the mode control inputs are controlled by registered logic in the Xilinx CPLD under the direction of software.
RAM
Access to the 32K SRAM is shared by the MCU and the video display generator. This is accomplished by providing tri-state buffers between the address and data lines from the MCU, and synchronizing the operation of the VDG to the MCU. All buffering and synchronization logic is performed by the CPLD.
Normally the MCU address buffers are disabled so that the VDG address is being supplied to the RAM and the RAM data is supplied to the VDG. However, during an MCU access of the RAM (E is high), the MCU address buffers in the CPLD are enabled and the MS* line of the VDG is asserted low to disable the MC6847 address lines. This provides the MCU address to the RAM chip and allows an MCU read or write cycle to occur.
EEPROM
The MC-11 uses a single 32K x 8 EEPROM to store the BIOS code and a Microsoft Basic interpreter. The EEPROM is connected directly to the multiplexed address/data, however any possible contention is avoided by asserting the Chip Enable pin (CE*) for the device only during the high cycle of the E clock when a valid address is decoded by the CPLD.
The R/W line from the MCU is also connected to the EEPROM, allowing the chip to be programmed in-system. The Output Enable (OE*) pin of the EEPROM is connected to pin PA5 of the MCU. This output-only port pin is low following reset and inhibits writing to the EEPROM under normal conditions. A software routine running exclusively from RAM can set the PA5 output high to allow a write cycle to be recognized by the EEPROM.
PS2 KEYBOARD
A controller for interfacing with a PS2 keyboard is implemented in an ATtiny84A micro controller. The controller translates up/down key events into signals that are sent to the Xilinx CPLD. The CPLD is programmed to simulate the keyboard matrix of a TRS-80 MC-10 and provides compatibility with existing software written for the MC-10.
Additionally, the ATiny controller is connected to the built-in UART of the 68HC11 allowing software written specifically for this SBC to directly receive and process up/down events from the keyboard.